Method to increase substrate potential in MOS transistors used in ESD protection circuits

ABSTRACT

An integrated circuit located between isolation trenches at the surface of a semiconductor chip comprising a first well of a first conductivity type having a first resistivity. This first well has a shallow buried region of higher resistivity than the first resistivity, extending between the isolation trenches and created by a compensating doping process. The circuit further comprises a second well of the opposite conductivity type extending to the surface between the isolation trenches, having a contact region and forming a junction with the shallow buried region of the first well, substantially parallel to the surface. Finally, the circuit has a MOS transistor located in the second well, spaced from the contact region, and having source, gate and drain regions at the surface. This space is predetermined to create a small voltage drop in I/O transistors for conditioning signals and power to a pad, or large voltage drops in ESD circuits for protecting the active circuitry connected to a pad. In the first embodiment, the space includes a dummy gate; in the second embodiment, an isolation region; in the third embodiment, the space a protected, stable surface.

FIELD OF THE INVENTION

[0001] The present invention is related in general to the field ofelectronic systems and semiconductor devices, and more specifically tostructure and fabrication methods of MOS transistors, which have anincreased substrate potential for improved ESD protection.

DESCRIPTION OF THE RELATED ART

[0002] Integrated circuits (ICs) may be severely damaged byelectrostatic discharge (ESD) events. A major source of ESD exposure toICs is from the charged human body (“Human Body Model”, HBM); thedischarge of the human body generates peak currents of several amperesto the IC for about 100 ns. A second source of ESD is from metallicobjects (“machine model”, MM); it can generate transients withsignificantly higher rise times than the HBM ESD source. A third sourceis described by the “charged device model” (CDM), in which the IC itselfbecomes charged and discharges to ground in the opposite direction thanthe HBM and MM ESD sources. More detail on ESD phenomena and approachesfor protection in ICs can be found in A. Amerasekera and C. Duvvury,“ESD in Silicon Integrated Circuits” (John Wiley & Sons LTD. London1995), and C. Duvvury, “ESD: Design for IC Chip Quality and Reliability”(Int. Symp. Quality in El. Designs, 2000, pp. 251-259; references ofrecent literature).

[0003] ESD phenomena in ICs are growing in importance as the demand forhigher operating speed, smaller operating voltages, higher packingdensity and reduced cost drives a reduction of all device dimensions.This generally implies thinner dielectric layers, higher doping levelswith more abrupt doping transitions, and higher electric fields—allfactors that contribute to an increased sensitivity to damaging ESDevents.

[0004] The most common protection schemes used inmetal-oxide-semiconductor (MOS) ICs rely on the parasitic bipolartransistor associated with an nMOS device whose drain is connected tothe pin to be protected and whose source is tied to ground. Theprotection level or failure threshold can be set by varying the nMOSdevice width from the drain to the source under the gate oxide of thenMOS device. Under stress conditions, the dominant current conductionpath between the protected pin and ground involves the parasitic bipolartransistor of that nMOS device. This parasitic bipolar transistoroperates in the snapback region under pin positive with respect toground stress events.

[0005] The dominant failure mechanism, found in the nMOS protectiondevice operating as a parasitic bipolar transistor in snapbackconditions, is the onset of second breakdown. Second breakdown is aphenomenon that induces thermal runaway in the device wherever thereduction of the impact ionization current is offset by the thermalgeneration of carriers. Second breakdown is initiated in a device understress as a result of self-heating. The peak NMOS device temperature, atwhich second breakdown is initiated, is known to increase with thestress current level.

[0006] Many circuits have been proposed and implemented for protectingICs from ESD. One method that is used to improve ESD protection for ICsis biasing the substrate of ESD protection circuits on an IC. Suchsubstrate biasing can be effective at improving the response of amulti-finger MOS transistor that is used to conduct an ESD discharge toground. However, substrate biasing can cause the threshold voltages fordevices to change from their nominal values, which may affect deviceoperation. In addition, substrate biasing under steady-state conditionscauses heat generation and increases power losses.

[0007] Solutions offered in known technology require additional ICelements, silicon real estate, and/or process steps (especiallyphotomask alignment steps). Their fabrication is, therefore, expensive.Examples of device structures and methods are described in U.S. Pat. No.5,539,233, issued Jul. 23, 1996 (Amerasekera et al., “Controlled LowCollector Breakdown Voltage Vertical Transistor for ESD ProtectionCircuits”); U.S. Pat. No. 5,793,083, issued Aug. 11, 1998 (Amerasekeraet al., “Method for Designing Shallow Junction, Salicided NMOSTransistors with Decreased Electrostatic Discharge Sensitivity”); U.S.Pat. No. 5,940,258, issued Aug. 17, 1999 (Duvvury, “Semiconductor ESDProtection Circuit”); U.S. Pat. No. 6,137,144, issued Oct. 24, 2000, andU.S. Pat. No. 6,143,594, issued Nov. 7, 2000 (Tsao et al, “On-Chip ESDProtection in Dual Voltage CMOS); and U.S. patent application Ser. No.09/456,036, filed Dec. 3, 1999 (Amerasekera et al., “ElectrostaticDischarge Device and Method”).

[0008] With the continued scaling in deep submicron technologies, it isimportant to search for ways to increase the strength of bipolar turn-onof nMOS transistors used in ESD protection circuits based on snap-backcharacteristics. In addition, the challenge of cost reduction implies adrive for minimizing the number of process steps, especially a minimumnumber of photomask steps, and the application of standardized processconditions wherever possible. These constraints should be kept in mindwhen additional process steps or new process conditions are proposed toimprove ESD insensitivity without sacrificing any desirable devicecharacteristics. An urgent need has, therefore, arisen for a coherent,low-cost method of enhancing ESD insensitivity without the need foradditional, real-estate consuming protection devices. The devicestructure should further provide excellent electrical performance,mechanical stability and high reliability. The fabrication method shouldbe simple, yet flexible enough for different semiconductor productfamilies and a wide spectrum of design and process variations.Preferably, these innovations should be accomplished without extendingproduction cycle time, and using the installed equipment, so that noinvestment in new manufacturing machines is needed.

SUMMARY OF THE INVENTION

[0009] The present invention describes an integrated circuit locatedbetween isolation trenches at the surface of a semiconductor chipcomprising a first well of a first conductivity type having a firstresistivity. This first well has a shallow buried region of higherresistivity than the first resistivity; the region extends between theisolation trenches. The circuit further comprises a second well of theopposite conductivity type extending to the surface between theisolation trenches, having a contact region and forming a junction withthe shallow buried region of the first well, substantially parallel tothe surface. Finally, the circuit has a MOS transistor located in thesecond well, spaced from the contact region, and having source, gate anddrain regions at the surface. This space is predetermined to create asmall voltage drop in I/O transistors for conditioning signals and powerto a pad, or large voltage drops in ESD circuits for protecting theactive circuitry connected to a pad. The space may have a linear ormeandering outline.

[0010] In the first embodiment of the invention, the space between thecontact and the source includes a dummy gate. In the second embodiment,the space includes an isolation region. In the third embodiment, thespace includes a protected, stable surface. In all embodiments, theregion of higher resistivity may have a resistivity about an order ofmagnitude higher than the first resistivity, and this higher resistivityis brought about by a compensating doping process according to theinvention.

[0011] The dummy gate structures of the first embodiment are formedconcurrently with the MOS gate structures. Consequently, thedistribution of the subsequently implanted ions is modulated so that thejunction between the second well and the region of higher resistivity ofthe first well has variable distance to the chip surface in accordancewith the configuration of the transistor gate and dummy gate structures.

[0012] The isolation region in the space between contact and source ofthe second embodiment is formed before second-well ion implant.Consequently, the second well has to be created by ions implanted withhigher energy than in the first embodiment and the junction between thesecond well and the region of higher resistivity of the first well has agreater distance from the surface. This distance, however, is variablein accordance with the configuration of the transistor gate and theisolation region.

[0013] In the third embodiment, the distance of the junction to thesurface varies in accordance with the transistor gate structure.

[0014] It is a technical advantage of the present invention that theelectrical substrate resistance, and the equivalent voltage drop,generated by the distance discussed above can be designed for severalapplications:

[0015] A small substrate resistance operates in an I/O transistor tocondition signals and power to a pad so that the substrate current noiseis blocked to get to the rest of the circuit, or that sensitive, non-I/Ocircuits are shielded from substrate current noise.

[0016] A large substrate resistance, and thus large voltage drop,operates in an ESD circuit to protect-the active circuitry connected toa pad.

[0017] The circuit of the present invention is electrically connected sothat the source is connected to Vss (ground) potential; the drain to padpotential; the contact region to Vss (ground) potential; and the firstwell to Vdd potential. The operation of the MOS transistor is such thatthe voltage drop is caused by the part of the drain avalanche currentflowing through the second well to the contact region through theresistance of the second well. When that resistance is small, thevoltage drop conditions signal and power to the pad. When thatresistance is large, the voltage drop de-biases the junction between thesecond well and the low-doped portion of the first well. As aconsequence, the lateral transistor formed by drain, second well, andcontact is turned on and the ESD protection of the pad is greatlyenhanced.

[0018] In one embodiment of the invention, the first conductivity typeis n-type and the MOS transistor is an nMOS transistor. The presentinvention is equally applicable to pMOS transistors; the conductivitytypes of the semiconductor and the ion implant types are simplyreversed.

[0019] It is another technical advantage of the present invention thatthe same photomask and alignment step can be used for severalfabrication process steps, thus reducing fabrication cost. Specifically,the ion implantation steps for creating the iso-p-well, the drainextension, and the transistor Vt adjustment are consecutively performedthrough the same photoresist window.

[0020] Another technical advantage of the present invention is theflexibility in creating the different substrate resistances discussedabove. Instead of employing the second well of opposite conductivitytype, a separate well of the first conductivity type can be used.

[0021] The technical advances represented by the invention, as well asthe aspects thereof, will become apparent from the following descriptionof the preferred embodiments of the invention, when considered inconjunction with the accompanying drawings and the novel features setforth in the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0022]FIG. 1A is a simplified and schematic cross section through alateral MOS transistor, illustrating the current flow at anelectrostatic discharge event, with the ground contact of the substratecurrent Isub at the back of the device.

[0023]FIG. 1B is a still more simplified cross section through a MOStransistor analogous to FIG. 1A yet with the ground contact of thesubstrate current Isub located at the surface.

[0024]FIG. 2 is a schematic plot of drain (collector) current, on alogarithmic scale, as a function a drain voltage, on a linear scale,illustrating the onset of the second breakdown phenomenon.

[0025]FIGS. 3A and 3B represent schematic cross sections of a lateralMOS transistor according to the first embodiment of the invention,including a dummy gate as a spacing tool. In FIG. 3A, this dummy gate isdesigned to operate in an ESD protection circuit; in FIG. 3B, this dummygate is designed to operate in an I/O transistor for conditioningsignals and power to a pad.

[0026]FIGS. 4A and 4B represent schematic cross sections of a lateralMOS transistor according to the second embodiment of the invention,including an isolation region as a spacing tool. In FIG. 4A, thisisolation region is designed to operate in an ESD protection circuit; inFIG. 4B, this dummy gate is designed to operate in an I/O transistor forconditioning signals and power to a pad.

[0027]FIG. 5A is a simplified top view of an embodiment of theinvention, in which a separate well of the first conductivity typegenerates the desired substrate resistance.

[0028]FIG. 5B is a simplified cross section along line A-A′ of thestructure in FIG. 5A.

[0029]FIG. 6A is a simplified top view of another embodiment of theinvention, in which a separate well of the first conductivity typegenerates the desired substrate resistance.

[0030]FIG. 6B is a simplified cross section along line B-B′ of thestructure in FIG. 6A. FIG. 6B further shows a photomask window used forseveral ion implant steps, illustrating the low cost aspect of thepresent invention.

[0031]FIG. 7 is a schematic top view of a transistor layout to achieve alarge substrate resistance for ESC protection.

[0032] FIGS. 8 to 13 are schematic and simplified cross sections of anMOS transistor illustrating individual process steps in the fabricationflow according to the invention.

[0033]FIG. 11A and 11B illustrate the multiple use of a photomask windowin the transistor process flow, emphasizing the low cost aspect of thepresent invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0034] The present invention is related to U.S. Patent Application No.60/263,619, filed on Jan. 23, 2001 (Salling et al., “Structure andMethod of MOS Transistor having Increased Substrate Resistance”).

[0035] The impact of the present invention can be most easilyappreciated by highlighting the shortcomings of the known technology.The schematic cross section of FIG. 1A illustrates a commonly usedintegrated circuit (IC) component 100 in an ESD protection circuit,namely an nMOS transistor which operates in the mode of a lateralbipolar npn transistor during an ESD event and provides a low impedancecurrent path to ground. The IC is formed in a semiconductor of a “firstconductivity” type; in the example of FIG. 1A, this “first conductivity”is p-type, the MOS transistor is an nMOS transistor, and the lateralbipolar transistor is an npn transistor. In present manufacturing, thefirst conductivity type semiconductor is created by the net doping dueto a “substrate” and a “well”.

[0036] As defined herein, the term “substrate” refers to the startingsemiconductor wafer. In present manufacturing, the substrate typicallyhas p-type doping. For clarity, this case is also selected as the basisfor the following discussions. It should be stressed, however, that theinvention and all description also cover the case where the substratehas n-type doping. In FIG. 1A, the substrate is designated 101.Frequently, but not necessarily, an epitaxial layer 102 of the sameconductivity type as the substrate has been deposited over the substrate101; in this case the term “substrate” refers to epitaxial layer 102plus starting semiconductor 101. For the conductivity example selectedfor FIG. 1A, a p-well 103 has been formed by localized acceptor ionimplantation and annealing. An n-plus source region 104 (the emitter ofthe bipolar transistor) and drain region 105 (the collector of thebipolar transistor) were formed by shallow ion implants of donors. Thesurface between the emitter 104 and the collector 105 is covered by gateoxide layer 106. Layers 107, 108, 109, and 110 provide metallic contactsto the gate, emitter, collector and the wafer backside, respectively.

[0037]FIG. 1A further shows that emitter 108, gate 107 and waferbackside 110 are electrically connected to ground potential (0 V). Apositive voltage spike at the collector, as caused by an ESD event,applies a reverse bias to the collector/base junction; the base is thesubstrate 101 (in some devices, epitaxial layer 102 plus the substrate101); the depletion layer of the space charge region is designated 120.When the electric field in the depletion region 120 exceeds thebreakdown field, avalanching occurs and forms electron/hole pairs.Electrons flow into the collector, and holes flow into the p-type base.

[0038] This hole current I-sub flows from the collector junction throughthe substrate to the backside contact 110, causing a voltage drop acrossthe resistors R-pwell and R-sub, which positive (forward) biases theemitter/base junction. This emitter forward bias is proportional to theeffective “substrate resistance” equal to the sum of the resistancecomponents in the current path, which are schematically shown as R-pwelland R-sub in FIG. 1A. Those of the electrons injected from the emitterinto the base which reach the collector depletion layer will participatein the avalanche mechanism.

[0039] In the schematic cross section of FIG. 1B, the same layout andelectrical scenario as in FIG. 1A is depicted with the exception thatthe ground contact for the substrate current Isub is located at thesurface instead of at the backside of the device. This arrangement ofFIG. 1B is frequently used in circuit designs.

[0040] The electron concentration will be multiplied in accordance withthe electric field dependent avalanche multiplication factor. Theresulting reduction of the device impedance is reflected in a “snapback” 201 in the current-voltage characteristic, which corresponds to a“turn on” of the bipolar transistor. FIG. 2 plots the collector (ordrain) current I (on a logarithmic scale) as a function of drain voltageV (on a linear scale). As illustrated in FIG. 2, this snap-back 201occurs at the collector/drain voltage Vt1 with an associatedcollector/drain current It1. The field dependence of the avalanchemultiplication factor is responsible for establishing a new stablecurrent/voltage equilibrium 202. At high electron injection levels, baseconductivity modulation also contributes towards making the deviceimpedance positive again. It should be mentioned that the lateral npntransistor also protects against negative ESD pulses. The collector 105(in FIG. 1A) now acts as emitter and diverts the ESD current to thebackside substrate contact 110 and to the now reverse biased emitter104, which now acts as collector.

[0041] The current carrying capability of the device is limited bythermal effects in the avalanching collector depletion layer. A numberof effects (such as the increase of intrinsic carrier concentration, areduced carrier mobility, a decrease in thermal conductivity, and alowering of the potential barrier for tunnel currents) contribute to theonset of the second (thermal) breakdown (203 in FIG. 2). The secondbreakdown trigger current It2 is very sensitive to the device design,especially the doping profiles. Second breakdown results in junctionmelting and in an irreversible increase in leakage currents. It must,therefore, be avoided for normal device operation.

[0042] It is important for the present invention to conclude from FIGS.1A and 1B and the above discussion of FIG. 2 that increasing theresistors R-pwell and/or R-sub will lead to an earlier turn-on of theemitter and to a reduction of the current contribution of the avalanchemechanism. This is reflected in an increase of the second breakdownthreshold current It2. As was pointed out in the above-referencedpublication by K. Bock et al., the p-well resistance R-pwell, and thusIt2, can be modified by the p-well doping. However, known technologyrecommended only a lower substrate (or epitaxial) doping or a lowerimplant dose as methods to increase the p-well resistance.

[0043] The structure and design of the MOS transistor having thepredetermined value of the substrate resistance, and thus voltage drop,is discussed in FIGS. 3 to 7 for several embodiments of the presentinvention. Furthermore, applications of the invention to ESD circuits aswell as generalized I/O transistors are indicated. The flexible andeconomical method for fabricating the embodiments according to theinvention is described in FIGS. 8 to 13. While the examples depictedembody the experimental conditions for an nMOS transistor, analogousconsiderations hold for the conditions of a pMOS transistor.

[0044] The schematic cross section of FIG. 3A (and analogous FIG. 3B)depicts a portion of a semiconductor chip surface with isolationtrenches 301 defining the region for a first well 302 of a firstconductivity type. In FIG. 3A, the first conductivity type is selectedto be n-type, so well 302 is an n-well. N-well 302 is fabricated byimplanting ions of a first conductivity type into the semiconductorsurface through a photoresist window between the isolation regions 301.The ions have high energy and high dose and create a resistivity for thefirst well 302 referred to as “first resistivity”.

[0045] Nested inside isolation trenches 301 is another set of isolationtrenches 303. A second photoresist layer is now deposited and a windowopened in this layer between isolation trenches 303. Through this newwindow, ions of the opposite conductivity type are implanted at highenergy and low dose so that they partially compensate for the doping ofthe well 302 in the region between trenches 303. By this“counter-doping”, a region 304 of lower doping concentration (still ofthe first conductivity type) is created, which is embedded within well302, yet may have the same penetration depth. For the conductivity typeselected in FIG. 3A, region 304 is sometimes referred to as “buriedn-type layer”. Region 304 has a resistivity higher than the resistivityof the first well 302 (but still the same conductivity type).

[0046] In the surface-near region, between trenches 303 and extending tothe surface, is a second well 305, of the opposite conductivity type(p-type in FIG. 3A; “isolated p-well”). This second well has a contact306 (p+ in FIG. 3A) and forms a junction 307 with the buried layer ofthe first conductivity type (n-type in FIG. 3A). Junction 307 issubstantially parallel to the surface, but the distance of junction 307to the surface varies in accordance with the configuration of transistorgate and dummy gate structures, or isolations. As can be seen in FIG.3A, the junction 307 a does not penetrate as deep under the transistorgate and dummy gate structures—a consequence of the fabrication methodby ion implantation discussed below. Under electrical operatingconditions, well 305 represents a resistance for a current flowing fromthe MOS transistor to well contact 306; this resistance is called“substrate resistance” Rsub in the nomenclature of FIG. 1B.

[0047] A MOS transistor is located in well 305, having source 310, gate311 and gate isolation 312, and drain 313 at the surface. It isessential for the present invention that this MOS transistor is spacedfrom well contact 306. The space may be linear as in FIG. 3A (320) andFIG. 3B (321), or it may be configured meandering or in any othersuitable outline. The space is predetermined to create, under electricaloperating conditions, a voltage drop along Rsub for the current Isub(see FIG. 1B) from the MOS transistor to well contact 306.

[0048] The magnitude of the predetermined voltage drop depends on theapplication the integrated circuit depicted in FIGS. 3A and 3B. Thevoltage drop is intended to be large in ESD circuits for protecting theactive circuitry connected to pad 314, which is connected to drain 313.Consequently, the distance 320 in FIG. 3A is large in order to create alarge resistance Rsub. The voltage drop is intended to be small inelectrically isolated I/O transistors for conditioning signals or powerto a pad. Consequently, the distance 321 in FIG. 3B is small in order tocreate a small resistance Rsub. As a general structure, an electricallyisolated I/O transistor is distinguished because its substrate noise isblocked from getting to the rest of the circuit. It also can be appliedto sensitive, non-I/O circuits in order to shield them from substratenoise current.

[0049] In the first embodiment of this invention, the space between thewell contact 306 and the transistor source 310 includes a dummy gate. InFIG. 3A, the space 320 includes the dummy gate 315 (connected toVss/ground potential), which actually determines the dimension of space315. This space falls into the “large” category described above, sinceit is intended for an ESD circuit. In FIG. 3B, the space 321 includesdummy gate 335, which again determines the dimension of space 321. Thisspace falls into the “small” category described above, since it isintended for an electrically isolated I/O transistor. Accordingly, thesecond well 340, which determines Rsub, is shorter; in the otheraspects, the circuit in FIG. 3B is analogous to the circuit in FIG. 3A.

[0050] In the second embodiment of this invention, the space between thewell contact 306 and the transistor source 310 includes an isolationregion. In FIG. 4A, this isolation region, designated 401, determinesthe dimension of space 420. In FIG. 4B, the isolation region, designated402, determines the dimension of space 421. Space 420 falls into the“large” category, since it is intended for an ESD circuit. Space 421falls into the “small” category, since it is intended for anelectrically isolated I/O transistor.

[0051] As can be seen in FIGS. 4A and 4B, the second wells 405 and 440of the opposite conductivity (p-type; “isolated p-well”) have to be ionimplanted considerably deeper (farther away from the surface) due to thedepth of the isolation regions 401 and 402. Junction 407 issubstantially parallel to the surface, but the distance of junction 407to the surface varies in accordance with the configuration of transistorgate 311 and isolation structure 401, designated by 407 and 407 a inFIG. 4A.

[0052] Alternatively, the space between the well contact and thetransistor source may include just a protected surface (without dummygate or isolation region). It may be linear, meandering or have anyother suitable outline.

[0053] The electrical connection of the circuits in FIGS. 3A, 3B, 4A,and 4B are analogous as follows:

[0054] Transistor source 310 is connected to Vss (ground);

[0055] Transistor drain 313 is connected to pad potential;

[0056] Well contact 306 is connected to Vss (ground);

[0057] Well 302 is connected to Vdd;

[0058] The MOS transistor is operated such that a voltage drop is causedby the part of the drain avalanche current flowing to contact 306through resistance Rsub of second well 305/340/405/440,

[0059] whereby, when Rsub is small, the voltage drop conditions signaland power to the pad (314);

[0060] whereby, when Rsub is large, the voltage drop de-biases thejunction between second well and the low-doped portion 304 of the firstwell 302, turning-on the lateral transistor formed by drain 313, secondwell 305, and contact 306, and enhancing the ESD protection of said pad.

[0061] The schematic FIGS. 5A, 5B, 6A and 6B describe embodiments of theinvention for device cases, where design constraints do not provideenough space for the buried n-layer and the isolated p-well to createenough voltage drop. For these situations, the solution disclosed in theFIGS. utilizes an additional discrete n-well, which offers enoughadditional electrical resistance for Isub when it is electricallyconnected to the isolated p-well.

[0062]FIGS. 5A and 6A are schematic top views, and FIGS. 5B and 6B,respectively, are simplified cross sections of two examples of theseembodiments. FIG. 5B is taken along cut line A-A′ in FIG. 5A, and FIG.6B is taken along cut line B-B′ in FIG. 6A.

[0063] The embodiment of FIGS. 5A and 5B illustrates the example of ashallow isolated p-well. The same number has been given to the samerespective identity in FIG. 5A and 5B. 501 is the n-well and 502 thecounterdoped part of the n-well (buried n-layer) having higherresistivity. 503 is the n+ drain of the MOS transistor, connected to thepad. 504 is the (conductive poly-silicon of the) gate. 505 is the p+contact to the p-type isolated p-well 505 a. In the example of FIGS. 5Aand 5B, this isolated p-well is shallow and thus confined by the trenchisolation 506. Contact 505 is connected to the n+ source 507 of thetransistor, which also serves as one contact to the discreet n-well 501.The other contact to the discreet n-well is 508, which is connected toVss/ground potential. The length 501 a between contacts 507 and 508serves as the pre-determined substrate resistance Rsub.

[0064] The embodiment of FIGS. 6A and 6B illustrates the example of adeep isolated p-well. The same number has been given to the samerespective identity in FIG. 6A and 6B. 601 is the n-well and 602 thecounterdoped part of the n-well (buried n-layer) having higherresistivity. 603 is the n+ drain of the MOS transistor, connected to thepad. 604 is the (conductive poly-silicon of the) gate. 605 is the p+contact to the p-type isolated p-well 605 a. In the example of FIGS. 6Aand 6B, this isolated p-well is deep, this means deeper than the trenchisolation 606. Contact 605 is connected to the n+ contact 607 of the onecontact to the discreet n-well 501. The other contact to the discreetn-well is 608, which is connected to Vss/ground potential. The length601 a between contacts 607 and 608 serves as the pre-determinedsubstrate resistance Rsub. The source 609 of the MOS transistor is alsoconnected to Vss/ground potential.

[0065] Superimposed on the features of the finished device, FIG. 6Bshows the photomask 610 and the position of its window 610 a from aprevious process step in order to emphasize a cost saving feature of themanufacturing process used for the device. Photomask 610 is employed forthe ion implant steps creating the isolated p-well and the high-voltagedrain extension and the Vt adjust (n-type), discussed in more detail inFIG. 11B.

[0066] A modification of the device structures in FIGS. 5A and 6A isschematically shown in FIG. 7. The modification illustrated how apre-determined value for the resistance Rsub can be achieved by ameandering design of the isolated p-well. The n-well 701 is bordered bythe trench isolation 702. Embedded in the n-well is the MOS transistorwith n+ source 703, gate 704, and n+ drain 705. The photomask 706 forthe drain extension ion implant step is designed in a meandering layout706 a, resulting in a meandering configuration of the isolated p-well.The meandering layout results in a pre-determined high value for Rsub.The p+ contact of the p-well is 707.

[0067]FIG. 8 to 13 describe important steps of the manufacturing processflow of the embodiments, specifically of the embodiment illustrated inFIG. 3A.

[0068]FIG. 8: Depositing, between the isolation trenches 801 at thesurface 802 of a semiconductor chip, a first photoresist layer 803 overchip surface 802 and opening a window 803 a in this first layer betweenthe isolation regions in the surface;

[0069] implanting, at high energy and high dose, ions of a firstconductivity type into surface 802 through window 803 a, creating afirst well 804 of a first conductivity type. In the example of FIG. 8,the first conductivity type is n-type; n-type dopants may be selectedfrom a group consisting of arsenic, phosphorus, antimony, and bismuthThe energy of the ions is preferably suitable to create the first wellat a depth between 900 and 1100 nm;

[0070] removing the first photoresist layer 803;

[0071]FIG. 9: Depositing a second photoresist layer 901 over the chipsurface 802 and opening a window 901 a in the second layer 901 betweensecond isolation regions 903 in the surface 802, the second isolationregions 903 nested within the first isolation regions 801;

[0072] implanting, at high energy and low dose, ions of the oppositeconductivity type into surface 802 through window 901 a, creating, bypartial doping compensation, a region 904 of lower doping concentrationof the first conductivity type embedded in first well 804, resulting ina regional resistivity higher than the resistivity of the first well804. In the example of FIG. 9, the opposite conductivity type is p-type;p-type dopants may be selected from a group consisting of boron,aluminum, gallium, indium, and lithium. The energy of the ions ispreferably suitable to create the partially compensated region at adepth between 900 and 1100 nm;

[0073] removing the second photoresist layer 901;

[0074]FIG. 10: Forming the gate structures 1001 for an MOS transistorand 1002 for a dummy gate positioned in the surface space 1003 betweensecond isolation regions 903;

[0075]FIG. 11A: Depositing a third photoresist layer 1101 over the chipsurface and opening a window 1101 a in the third layer 1101 betweensecond isolation regions 903 in the surface 802;

[0076] implanting, at medium energy and medium dose, ions of theopposite conductivity type into the surface 802 through the window 1101a and through gate structures 1001 and 1002, creating a second well 1102of opposite conductivity type close to and substantially parallel to thesurface 802. The medium energy ions have an energy suitable for creatingthe second-well junction at a depth between 200 and 400 nm; theypreferably have a peak concentration from about 5·10E17 to 5·10E20 cm-3.

[0077]FIG. 11B: Implanting, at low energy and high dose, ions of thefirst conductivity type into the surface 802 through the window 1101 a,creating the drain extension regions 1103 of the MOS transistor;

[0078] implanting, at low energy and low dose, ions of the oppositeconductivity type into the surface 802 through the window 1101 a andthrough gate structures 1001 and 1002, adjusting the gate voltage Vt ofthe MOS transistor (not shown in FIG. 11B);

[0079] removing the third photoresist layer 1101;

[0080]FIG. 12: Forming insulating sidewalls 1201 on the gate 1001, andsidewalls 1202 on the dummy gate 1002;

[0081] implanting ions of the first conductivity type into the surface802 through the window 1210 a of fourth photoresist layer 1210, formingdeep source and drain regions 1203 of the MOS transistor; and

[0082]FIG. 13: Implanting ions of the opposite conductivity type intothe surface 802 through the window 1310 a of fifth photoresist layer1310, forming the contact region 1301 of the second well 1102 (p-typedeep source/drain implant in the example of FIG. 13).

[0083] The process flow may be modified to include annealing steps atelevated temperature after the high energy and/or the medium energyimplant steps.

[0084] While this invention has been described in reference toillustrative embodiments, this description is not intended to beconstrued in a limiting sense. Various modifications and combinations ofthe illustrative embodiments, as well as other embodiments of theinvention, will be apparent to persons skilled in the art upon referenceto the description. As an example, the semiconductor chip may be madefrom a material selected from a group consisting of silicon, silicongermanium, gallium arsenide, or any other semiconductor material used inintegrated circuit fabrication.

[0085] As another example, the step of implanting ions of the oppositeconductivity type at medium energy and medium dose is replaced by thestep of implanting ions of the opposite conductivity type atmedium-to-high energy and medium dose. In this process, the ion energyis suitable to create the second well junction with the region of higherfirst-well resistivity at a depth between 600 and 800 nm (see FIG. 4A).The peak ion concentration is preferably from about 5·10E19 to 5·10E20cm-3.

[0086] It is therefore intended that the appended claims encompass anysuch modifications or embodiments.

We claim:
 1. An integrated circuit located between isolation trenches atthe surface of a semiconductor, comprising: a first well of a firstconductivity type having a first resistivity; said first well having ashallow buried region of higher resistivity than said first resistivity,said region extending between said isolation trenches; a second well ofthe opposite conductivity type extending to said surface between saidisolation trenches, having a contact region and forming a junction withsaid shallow buried region of said first well, substantially parallel tosaid surface; and a MOS transistor located in said second well, spacedfrom said contact region, and having source, gate and drain regions atsaid surface, wherein said space is predetermined to create a smallvoltage drop in I/O transistors for conditioning signals and power to apad, or large voltage drops in ESD circuits for protecting the activecircuitry connected to a pad.
 2. The circuit according to claim 1wherein said space is configured in linear or meandering or any othersuitable outline.
 3. The circuit according to claim 1 wherein said spaceincludes a dummy gate or an isolation region or an otherwise protectedsurface.
 4. The circuit according to claim 3 wherein said junctionvaries in distance to said surface in accordance with the configurationof said transistor gate and dummy gate structures, or isolation region.5. The circuit according to claim 1 further comprising an additionalwell of the first conductivity type electrically in series with saidwell of the opposite conductivity type so that the sum of theirelectrical resistances provides the large voltage drop in ESDapplications required for protecting the active circuitry connected tosaid pad.
 6. The circuit according to claim 1 wherein said semiconductorchip is made from a material selected from a group consisting ofsilicon, silicon germanium, gallium arsenide, and any othersemiconductor material used in integrated circuit fabrication.
 7. Thecircuit according to claim 1 wherein said first conductivity type isn-type and the semiconductor has a dopant species selected from a groupconsisting of arsenic, phosphorus, antimony, and bismuth.
 8. The circuitaccording to claim 1 wherein said region of higher resistivity may havea resistivity about an order of magnitude higher than said firstresistivity, where said higher resistivity is brought about by acompensating doping process, which uses, for an n-type firstconductivity, a dopant species selected from a group consisting ofboron, aluminum, gallium, indium, and lithium.
 9. The circuit accordingto claim 1 further comprising: an electrical connection of said sourceto Vss (ground) potential; an electrical connection of said drain tosaid pad potential; an electrical connection of said contact region toVss (ground) potential; an electrical connection of said first well toVdd potential; an operation of said MOS transistor such that a voltagedrop is caused by the part of the drain avalanche current flowing tosaid contact region through the resistance of said second well; whereby,when said resistance is small, said voltage drop conditions signal andpower to said pad; and whereby, when said resistance is large, saidvoltage drop de-biases said junction between said second well and saidlow-doped portion of the first well, turning-on the lateral transistorformed by drain, second well, and contact, and enhancing the ESDprotection of said pad.
 10. The circuit according to claim 9 whereinsaid Vdd potential is positive.
 11. The circuit according to claim 9wherein, under ESD conditions, said pad potential is positive and saiddrain avalanche flow comprises holes.
 12. A method for fabricating anintegrated circuit located between isolation trenches at the surface ofa semiconductor chip for, comprising the steps of: depositing a firstphotoresist layer over said chip surface and opening a window in saidfirst layer between first isolation regions in said surface; implanting,at high energy and high dose, ions of a first conductivity type intosaid surface through said window, creating a first well of a firstconductivity type; removing said first photoresist layer; depositing asecond photoresist layer over said chip surface and opening a window insaid second layer between second isolation regions in said surface, saidsecond isolation regions nested within said first isolation regions;implanting, at high energy and low dose, ions of the oppositeconductivity type into said surface through said window, creating, bypartial doping compensation, a region of lower doping concentration ofthe first conductivity type embedded in said first well, resulting in aregional resistivity higher than the resistivity of the first well;removing said second photoresist layer; forming the gate structures fora MOS transistor positioned in the surface space between said secondisolation regions; depositing a third photoresist layer over said chipsurface and opening a window in said third layer between said secondisolation regions in said surface; implanting, at medium energy andmedium dose, ions of the opposite conductivity type into said surfacethrough said window and through said gate structures, creating a secondwell of opposite conductivity type close to and substantially parallelto said surface; implanting, at low energy and high dose, ions of thefirst conductivity type into said surface through said window, creatingthe drain extension regions of said MOS transistor; implanting, at lowenergy and low dose, ions of the opposite conductivity type into saidsurface through said window and through said gate structures, adjustingthe gate voltage Vt of said MOS transistor; removing said thirdphotoresist layer; forming insulating sidewalls on said gate, deepsource and drain regions of said MOS transistor, and contact region ofsaid second well, whereby said contact region is spaced from said MOStransistor by a predetermined distance.
 13. The method according toclaim 12 wherein said predetermined distance is selected to create asmall voltage drop in I/O transistors for conditioning signals and powerto a pad.
 14. The method according to claim 12 wherein saidpredetermined distance is selected to create a large voltage drop in ESDcircuits for protecting the active circuitry connected to a pad.
 15. Themethod according to claim 12 further comprising the step of: formingdummy gate structures concurrently with forming said MOS transistor gatestructures; thereby modulating the distribution of the subsequentlyimplanted ions so that the junction between said second well and saidregion of higher first-well resistivity varies in distance to saidsurface in accordance with the configuration of said transistor gate anddummy gate structures.
 16. The method according to claim 12, whereinsaid step of implanting ions of the opposite conductivity type at mediumenergy and medium dose is replaced by the step of implanting ions of theopposite conductivity type at medium-to-high energy and medium dose. 17.The method according to claim 16, after the step of forming the gatestructures further comprising the step of: forming an isolation regionat said surface, extending between said MOS transistor source region andsaid second-well contact region; thereby modulating the distribution ofthe subsequently implanted ions so that the junction between said secondwell and said region of higher first-well resistivity varies in distanceto said surface in accordance with the configuration of said isolationregion and said transistor gate structure.
 18. The method according toclaim 12 further comprising the step of annealing said high energyimplant at elevated temperature.
 19. The method according to claim 12wherein said implanting of medium energy ions comprises ions having anenergy suitable for creating the second-well junction at depth between200 and 400 nm, and a peak concentration from about 5·10E17 to 5·10E20cm-3.
 20. The method according to claim 17 wherein said implanting ofmedium-to-high energy ions comprises ions having an energy suitable forcreating the second-well junction at a depth between 600 and 800 nm, anda peak concentration from about 5·10E19 to 5·10E20 cm-3.
 21. The methodaccording to claim 12 wherein said implanting of high energy ionscomprises ions having an energy suitable for creating the first well andthe partially compensated region at a depth between 900 and 1100 nm.